QUIZ- Mixed Queries July 2019

1. An SoC contains CPU, DDR Controller , L1 Cache, I2C, SPI, DMA and Ethernet Controller . Incoming traffic on Ethernet controller has to be passed from Ethernet Controller to Memory connected via DDR Controller. This should be done without using CPU cycles. The best approach to achieve this will require

2. In Ethernet Controller , MAC communicates with PHY using :

3. I2C is a uni-directional two wire bus

4. I2C BUS supports multiple address recognition

5. Put   Cache, Flash, DDR, SDRAM in increasing order of speed. First device must be slowest one and last the fastest one.

6. The UART section responsible for bit-rate of any MCU is called

7. If SPI controller working as a slave device, Its input data will be

8. DDR controller is inialized in a Embedded system running linux by :

9. Select the the item not relevant with others in following

10. If you have to halt CPU based on some data comparison using SWD/JTAG based debugger, You need to use