QUIZ-ARM -

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1. User application will run in Thread mode. If any interrupt or exception event occurs, It will automatically enters in :

Background mode

Exception Error mode

Handler mode

Low power mode

2. If a core supports only Thumb and Thumb-2 instruction sets, then which one of the following is True :

Control register bit decides how many instruction bits to fetch

First 5-bits of half word-2(hw2) determine whether fetch or not first half word part.

First 5-bits of half word-1(hw1) determine whether fetch or not second half word part.

complete 32-bit instruction to be fetched

3. What is Industry standard for designing ARM micro-controller bare metal device driver ?

Cortex Microcontroller Software Interface Standard (CMSIS)

Cortex Software Interface Standard (CSIS)

Cortex Microcontroller Software Industry Standard (CMSIS)

Cortex Microcontroller Software Standard (CMSS)

4. Program counter in ARM Cortex M4 is

Run-time Instruction Memory Pointer

Run-time Instruction Execution Pointer

Counter to record total instructions executed

5. M in ARM Cortex -M series stands for :

ARM Multimedia core

Micro-Controller

ARM Multi-core device

6. STM32cubeMX is a :

Graphic tool to configure STM32 microcontroller

STM32 Multi-core evaluation platform

STM32 programming IDE

STM32 cube debugger

7. What are the following true regarding Artificial Intelligence using STM32 ?

No, AI require very high performance CPU

Yes, AI at Edge can be done with STM32 cube

It will require additional high end CPU .

Yes, It is supported by STM32cube,AI

8. APSR -Application program status register can be accessed from :

Both Privileged and Unprivileged level

Unprivileged level only

Privileged level only

9. CMSIS is a ———- to integrate third-party software

IDE

Compiler

Debugger

Framework

10. T32 in ARM architecture is :

Thumb Instruction set) Instructions with 16-bit size instructions.

Thumb Instruction set) Instructions with both 16 and 32-bit size instructions.

Thumb Instruction set) Instructions with 32-bit size instructions.

ARM core based TI SoC

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