QUIZ- Mixed Queries July 2019

Posted by

This particular QUIZ has mixed questions . Click on the subject line.

This is a simple quiz with mixed embedded topics.

1. An SoC contains CPU, DDR Controller , L1 Cache, I2C, SPI, DMA and Ethernet Controller . Incoming traffic on Ethernet controller has to be passed from Ethernet Controller to Memory connected via DDR Controller. This should be done without using CPU cycles. The best approach to achieve this will require


2. I2C BUS supports multiple address recognition


3. The UART section responsible for bit-rate of any MCU is called


4. DDR controller is inialized in a Embedded system running linux by :


5. If you have to halt CPU based on some data comparison using SWD/JTAG based debugger, You need to use


6. If SPI controller working as a slave device, Its input data will be


7. Put   Cache, Flash, DDR, SDRAM in increasing order of speed. First device must be slowest one and last the fastest one.


8. Select the the item not relevant with others in following


9. Following registers in an SoC can’t be memory mapped


10. In Ethernet Controller , MAC communicates with PHY using :


Question 1 of 10

Please provide your feedback regarding this. Also subscribe  Embedkari for other interesting topics. .

Embedkari has introduced its first low cost technical training .

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.