QUIZ- Mixed Queries July 2019

1. DDR controller is inialized in a Embedded system running linux by :

2. In Ethernet Controller , MAC communicates with PHY using :

3. I2C is a uni-directional two wire bus

4. The UART section responsible for bit-rate of any MCU is called

5. Put   Cache, Flash, DDR, SDRAM in increasing order of speed. First device must be slowest one and last the fastest one.

6. Select the the item not relevant with others in following

7. If you have to halt CPU based on some data comparison using SWD/JTAG based debugger, You need to use

8. I2C BUS supports multiple address recognition

9. If SPI controller working as a slave device, Its input data will be

10. Following registers in an SoC can’t be memory mapped