RISC – AVR, Power

 

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Key Takeaway 

Basic understanding of RISC(Reduced Instruction Set Computing)and the various RISC architecture based cpu cores and devices. This includes AVR,PowerPC and Power  Architecture

AVR

Lets try to understand the simple and popular AVR core first. I discussed AVR from programming perspective earlier in this blog. Lets have a quick look to understand the single level instruction pipeline. 

AVR based microcontrollers are further divided into TinyAVR,MegaAVR,XMegaAVR depending on flash size and other attributes.

Atmel/Microchip  has 32-bit AVR32 architecture as well but now they have switched to ARM .

What is basic RISC concept ?

Simple instructions with execution time one clock cycle. Work is divided between LOAD and STORE units. Cycles per instruction are reduced by overlapped instruction execution using pipeline.

This link explains how pipeline stages utilize all the hardware units(Fetch,Decode,Execute,Memory read/write,Write back) in the fifth cycle and after that all instructions take one cycle effectively. Only Pipeline filling takes time. This is similar to any production pipe line or even normal water pipe line.

First RISC based system was IBM’s PC/XT in 1980. Lets look into major milestones and where it stands today

POWER based RISC development

1980: POWER by IBM

Performance Optimization With Enhanced RISC. An old microprocessor instruction set architecture designed by IBM. IBM POWER Instruction Set Architecture

1992: PowerPC

Power Performance Computing. A 32/64-bit instruction set for microprocessors derived from the POWER ISA by AIM (Apple , IBM and Motorola). 

2002: Book-E 

Motorola and IBM also made the “Book E”[2] extension of PowerPC, used in embedded implementations: Motorola’s PowerQUICC processors .

Here QUICC stands for Quad Integrated Communication Controller. 

2004: Power Architecture

IBM and 15 other companies founded Power.org as an organization and developed  Power Architecture technology.[6] Freescale joined Power.org in 2006 and Power.org released the Power ISA version 2.03.[8] in September 2006

2013: OpenPOWER

IBM founded the OpenPOWER Foundation opening up for licensing of their future POWER8 processor and related technologies. The OpenPOWER Foundation released the Power ISA version 3.0 in December 2015

PowerPC architects defined three books to prevent user application software to tied a supervisory level architecture. These books are available  here.  

The Power Architecture specification is divided into five parts, called “books”.

  • Book I (UISA)User Instruction Set Architecture covers the base instruction set available to the application programmer.  Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. 
  • Book II (VEA)Virtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
  • Book III (OEA)Operating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It’s divided into two parts.
    • Book III-S – Defines the supervisor instructions used for general purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
    • Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
  • Book VLEVariable Length Encoded Instruction Architecture defines alternative instructions and definitions from Book I-III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big endian byte ordering.

Freescale/NxP  specific Power cores can be divided into two categories

  • Classic PowerPC
    • e300 and e600

  • Book-E based
    • e200,e500   are based on Power ISA v.2.03  
    • e5500 is based on Power ISA v.2.06
    • e6500 is based on Power ISA v.2.07

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