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Lessons
Introduction
Tools
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Verilog -day 1
ConceptC/C++Verilog Equivalent Variable declarationint a;reg a; / wire a; Assignmenta = b;a = b; (inside procedural blocks) or assign a […]
Verilog – day2
Control Flow (Loops) Only inside procedural blocks (always or initial): verilogCopyEditfor (i = 0; i < 10; i = i […]
Verilog – Introduction
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Verilog Experiment 1
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Data Types
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Modules
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Modelling
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HDL Fundamentals
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Operator part 1
Operator ;”
Operator Part 2
Operator Part 2 ;”
Test1
Test2
Test Bench
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Fast Adder
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