*******In Progress ***************
Lessons
Introduction
Tools
;”
Verilog -day 1
Concept C/C++ Verilog Equivalent Variable declaration int a; reg a; / wire a; Assignment a = b; a = b; […]
Verilog – day2
Control Flow (Loops) Only inside procedural blocks (always or initial): verilogCopyEditfor (i = 0; i < 10; i = i […]
Verilog – Introduction
;”
Verilog Experiment 1
;”
Data Types
;”
Modules
;”
Modelling
;”
HDL Fundamentals
;”
Operator part 1
Operator ;”
Operator Part 2
Operator Part 2 ;”
Test1
Test2
Test Bench
;”
Fast Adder
;”
Flow Control
;”