ARM Instruction Set Classification

This article discuss various ARM instruction sets including ARM, Thumb, Thumb-2 and latest nomenclature T32, A32, A64.  It also discuss various execution states and logic used.

This is in continuation of last article ARM Cortex-M4

Why Thumb instruction set was required ? 

One of the common thing you will come across in Embedded System design to choose between Memory and Instruction execution speed.  A similar challenge to reduce code memory was addressed by compressing most frequently used ARM 32-bit instructions to 16-bit instructions called Thumb. There is a separate processor state for this , with a mechanism to switch between ARM and Thumb state.

The Thumb instruction will be decompressed at run time  to equivalent ARM instruction without loosing performance.

Another advantage of Thumb instruction is low power consumption because  of16-bit system bus to fetch the instruction.. So less memory , system bus will also save PCB size. This makes it suitable for low end microcontrollers.

If you analyze the ARM history   , You may notice  introduction of Thumb instruction in ARMv4T ISA basedARM7T family  core  ARM7TDMI

Why Thumb-2 instruction set was introduced ? 

Thumb covered only most commonly used instructions  only not complete ARM instructions , which limited it’s features .

Later Thumb-2  was introduced in ARMv6T2 ISA based ARM11 family core ARM1156T2-S . It covered almost all ARM instructions. Thumb-2 has both 16 and 32-bit encoded instructions. These instructions can be intermixed to achieve almost equal or better performance than ARM instruction mode with code density equivalent to  original Thumb  ISA 

This is something similar to variable length instruction set architecture I discussed in PowerPC and RISCV.

Most ARMv7-A (and earlier) implementations support two instruction sets, the 32-bit ARM instruction and 32/16-bit Thumb instruction set.

ARMv8-A 

ARMv8-A AArch32 execution mode continues to support these two instruction sets, but they are renamed as A32 and T32 respectively. AARCH32  was introduced in ARMv8A ISA  based Cortex-A family  core  Cortex-A32

ARMv8-A additionally introduces the A64 instruction set, used in the AArch64 execution state. AARCH64 was introduced in ARMv8A ISA  based Cortex-A family  core  Cortex-A35

The changes between ARMv8 T32/A32 Instruction Sets and ARMv7-A instruction set can be found in chapter ‘ARMv8 Changes to the T32 and A32 Instruction Sets’ of ARMv8 Architecture Reference Manual.

How different kinds of Instruction sets were recognized by processor ?

All the instruction sets ARM, Thumb, AARCH32, AARCH64 execute in respective execution state. ARMv7A or older devices used  CPSR or xPSR  combined program status register register bit T .  ARMv8 use SPSR_EL1 register bits  to identify different execution states as shown below. SPSR is here Saved Program Status Register.

How  can  single Thumb  state distinguish between 16 and 32-bit instructions ? 

If a core supports only Thumb and Thumb-2 instruction sets. First 5-bits of  half word-1(hw1) determine whether fetch or not second half word part.

Reference :

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471i/CHDFEDDB.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0801b/IBAIEGDJ.html

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