Programming with ARM @Cortex-M4 based STM32 Nucleo

This provides information related to ARM Cortex-M4 features , Modes, Registers etc. I have discussed importance of multiple stack pointers and privilege levels. STM32 Nucleo-L4R5ZI board is taken for this case study.

This is in continuation of last blog ARM

Where to start learning ARM architecture ?

Let me take example of three different ARM family based SoCs . Following table provides different features of specifications, the CPU implementation and SoC based on that from three different semiconductor companies.

This comparison is just to understand different ARM family features. I understand that in terms of product/pricing , this is not Apple-to-Apple comparison. You may take analogy with sticky note, Notepad and Word  Windows programs in terms of features/requirement.

Cortex-M4 @STM32

Following are three important aspects related to software architecture :

• User application will run in Thread mode. If any interrupt or exception event occurs, It will automatically enters in Handler mode. After executing Interrupt Service Routine, It will return to Thread mode
• Unprivileged level helps in restricting  user application  to access many system critical resources.
• Two stack pointers help in protecting OS stack from application and also helps in managing  multi-process applications

How two stack pointers help in Multi-process Applications  ?

Lets assume process-1 is using stack region pointed by PSP1 and process-2 using stack region pointed by PSP2 . Kernel is using MSP  and these processes or tasks are using PSP .

Now when process-1 starts running , PSP register  will be assigned PSP1 . When operating system scheduler interrupt occurs , control will be automatically passed to interrupt handler which itself uses MSP register for stack. Interrupt handler will assign PSP2 to PSP register . After returning from Handler mode, process state will be automatically changed to Thread mode and it will start using PSP .

This overall process will make context switching between two processes fast and independent of handler mode stack pointer i.e. MSP .

Cortex-M4 Registers Overview

I will go through necessary registers first to make learning simpler. Following registers (r0-r12), PSP, LR and PC can be accessed with unprivileged level as well.

• Registers r0-r12 are for data manipulation in ALU
• Low Registers can be accessed by all instructions
• High Registers not accessible by all 16-bit encoded instructions.
• Stack Pointer– Run time temporary data memory Pointer
• Link Register – Receives return address from PC whenever BL and Blx instruction executed. Also used for exception return
• Program Counter -Run-time Instruction Memory Pointer

 

• XPSR -Combined Program Status Register
  • APSR -Application program status register. It can be accessed from Unprivileged level as well.
    Flags from previous instructio executions
  • IPSR – Interrupt program status register (Read Only)
    Number of the current ISR
  • EPSR -Execution program status register(Read Only)
    Thumb state bit, and the execution state bits for either the:
    • If-Then (IT) instruction
    • Interruptible-Continuable Instruction (ICI)
• CONTROL
  • FPCA – Floating Point Context Active
  • SPSEL- MSP or PSP
  • nPRIV -Thread mode Privilege
• MSP – Handler Mode always use this. By default, only MSP is being used for both Thread and Handler mode.
• PSP– Thread Mode can be configured to use MSP or PSP using CONTROL register

Reference

• • ARM Infocenter Documentation   
  • ST Documentation

Next Article   ARM Instruction Set Classification

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This particular post is discussed  at ARM Cortex-M4